ביום ג', ה-18 במאי 2021, תקיים חברת סינופסיס (Synopsys) וובינר בתחום האצת הבדיקה של אבות טיפוס של רכיבי SoC באמצעות FPGA כלי ניתוח ייעודיים הבודקים את התכנון. הוובינר, Enabling Faster Time to First Prototype using FPGA Synthesis Tools, יתקיים בשעה 20:00 לפי שעון ישראל.
FPGA prototyping is one of the main verification tools used when designing an SoC. There are many requirements for developing prototypes ranging from handling DesignWare IP to automated gated clock conversion. Synopsys’ ProtoSynthesis Software provides customers with the capability to develop a single FPGA prototype quickly and efficiently, and supports DesignWare IP and Unified Power Format (UPF).
This Synopsys webinar will cover: How to complete a gated clock conversion; Enabling DesignWare IP within an FPGA prototyping project; How to include power management intent in an FPGA prototype.
Speakers: Nilesh Shilankar and Poojitha Bommu
Nilesh Shilankar is Sr. Applications Engineer at Synopsys for FPGA-based synthesis software tools. Prior to joining Synopsys, Nilesh worked with leading semiconductor and EDA companies as a Product Engineer and Applications Engineer. Nilesh holds a bachelor’s degree in Electronics Engineering and has pursued a PG Diploma in VLSI from the Center for Development of Advanced Computing.
Poojitha Bommu is an Application Engineer for FPGA-based synthesis software tools in the Verification Group at Synopsys. She has 4 years of experience on Synopsys FPGA synthesis and prototyping tools. She has worked with many FPGA implementation and prototyping based customers to achieve their design requirements. She holds a BTech degree in Electronics and Communications from Amrita University, Bengaluru, India.