ביום ד', ה-13 בנובמבר 2024, תקיים חברת סינופסיס (Synopsys) וובינר בנושא תיכנון ואימות מודולי זיכרון המשובצים בתוך רכיבי SoC מודרניים. ההדרכה המקוונת תשודר בשעה 18:30 לפי שעון ישראל ותימשך 60 דקות. היא תתקיים תחת הכותרת: Memory Verification in Modern SoCs Using Formal Equivalence Checker.
Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy but limited coverage, while cell-based methods can't fully represent transistor-level behavior. Synopsys ESP, a custom circuit formal equivalence checker, addresses these challenges with its patented symbolic simulation technology, combining the power of formal methods with event-driven simulation for sequential equivalence checking. This approach dramatically enhances the quality of functional verification and boosts verification productivity.
Join our webinar to explore how Synopsys ESP provides a circuit-aware, easy-to-use solution for memory verification. An overview on ESP is provided along with Intel sharing their success using ESP for Content Addressable Memory (CAM).
Agenda:
- ESP Overview (10-15 mins) presented by Almitra Pradhan, Synopsys
- Intel usage of ESP for CAM (20-25 mins) presented by Anshuli Pandey, Intel
- Summary
- Q&A
Speakers:
Anshuli Pandey (left) is Circuit Design Engineering Manager in Central Memory Organization team in Intel. This team is responsible for providing Register File, ROM, Content Addressable Memory compilers for internal products and Foundry Services platform. She is an alumnus of BITS Pilani and has ~19 years of experience in Memory Design.
Almitra Pradhan (right) leads the ESP product development at Synopsys. She has 15 years of experience in EDA specializing in Transistor level EDA tools for custom digital design. She holds a Ph.D. from University of Cincinnati, Ohio in Electrical and Computer Engineering.
Speaker: Jim Schultz, senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification, design planning and design implementation on CPUs, networking and security chips. As a product engineer, he has supported design implementation, design planning and package design at various EDA companies.
Part II: Wednesday, November 29, 2023
Vivek Upadhyaya (right), Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom, Cadence, Intel, and STMicroelectronics, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut, UP.
