ביום ב', ה-9 בפברואר 2026, תקיים חברת סינופסיס (Synopsys) וובינר שיוקדש לבדיקות באמצעות סימולציה של עמידות השבב המתוכנן בפני תופעות של פריקת חשמל סטטי (ESD). התופעות האלה יכולות להרוס את השבב או מעגלים מסויימים בתוכו, ולכן חשוב לזהות ולאפיין אותן לפני המעבר לייצור. ההדרכה תתמקד בשימוש ב-Synopsys PathFinder-SC, אשר משמש לסימולציה והערכה של המערכת כולה (Full-Chip ו-Multi-Die), ולא רק של הטרנזיסטור הבודד או התת-מערכת הנפרדת.
ההדרכה המקוונת תשודר בשעה 18:00 לפי שעון ישראל ותימשך 60 דקות. היא תתקיים תחת הכותרת:
Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC.
הסבר מורחב:
PathFinder-SC uses the same extraction and EM calculation engine with Synopsys RedHawk-SC certified by major foundries which can help detect potential silicon failures. Its layout-based debugging and compact modeling extend reliability from die to package to board. Seamlessly integrated into modern verification flows, PathFinder-SC empowers teams to accelerate signoff, mitigate risk, and deliver future-proof designs for HPC, AI/ML, and 5G/6G systems.
Join our PathFinder-SC webinar to see how you can:
- Perform pre-LVS, cell-based ESD checks early in the flow
- Handle full-chip and multi-die designs with cloud-native capacity
- Use a foundry certified solution and layout-based debugging for reliability from die to board
- Accelerate signoff, reduce risk, and future-proof your designs
דוברים:
Peter Tsai (left) is a Product Manager at Synopsys. He is focusing on ESD and reliability signoff for advanced designs. Prior to Synopsys, Peter held technical and customer-facing roles at Cadence, Siemens EDA, and AUO, developing expertise in analog/mixed-signal design, physical verification, and signoff flows.
Marc Swinnen (center) is a Product Marketing Manager at Synopsys. Before joining Synopsys, Marc worked at Ansys, Cadence, Azuro, and Sequence Design, where he gained experience with a wide array of digital and analog design tools.
Speaker: Diwakar Kumaraswamy, Technical Product Manager at Synopsys with over 15 years of experience in SoC design and high-speed interconnects. He specializes in PCIe architecture for AI and HPC, supporting next-generation connectivity solutions for advanced infrastructure.
Key benefits of migrating to PCIe 5.0
Speaker: Jim Schultz, senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification, design planning and design implementation on CPUs, networking and security chips. As a product engineer, he has supported design implementation, design planning and package design at various EDA companies.
