ביום ד', ה-30 באפריל 2025, תקיים חברת סינופסיס (Synopsys) וובינר בנושא תקן הקישוריות החדש PCIe 7.0 ומדוע החברות צריכות להכיר אותו ולאמץ אותו כבר עכשיו. ההדרכה המקוונת תשודר בשעה 20:00 לפי שעון ישראל ותימשך 60 דקות. היא תתקיים תחת הכותרת: PCIe 7.0? Understanding Why Now is the Time to Transition.

This session will explore the need of transitioning to PCIe 7.0 for chip-to-chip (C2C) connectivity. We will delve into how this transition impacts various use cases, including SSDs, network switches, and SuperNICs, highlighting the doubled data transfer rate of 128 GT/s per lane and its implications.

Gain insights into how PCIe 7.0 can improve SoC architectures by: Addressing challenges such as bifurcation, Providing 16X support in Gen 7 controllers, Discover key enhancements of PCIe 7.0, such as latency, power and error correction optimization, Reduced latency and Improved power efficiency.

Speakers:

למידע נוסף ורישום:

PCIe 7.0? Understanding Why Now is the Time to Transition

ביום ד' ה-17 ביולי 2024 תקיים חברת סינופסיס וובינר בתחום הבדיקות להבטחת איכות ייצור שבבים, במטרה להפחית את מספר הפגמים בקו הייצור (DPPM). הוובינר יתקיים בשעה 20:00 לפי שעון ישראל.

Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll also highlight the benefits of VC Z01X robust support of the SystemVerilog language. Finally, a practical flow discussion will equip viewers with best practices to get started.

Speakers:

Robert Ruiz, Product Management Director at Synopsys, and responsible for strategy and business growth of several verification products at Synopsys. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs). Robert has a BSEE degree from Stanford University. Kirankumar Karanam, Applications Engineer at Synopsys. He currently oversees various customer deployments of Synopsys FuSa verification solutions worldwide. He also works with Synopsys functional verification offerings such as VCS, Verdi, and more.

למידע נוסף ורישום:

Enhancing Manufacturing Test Flows with Synopsys VC Z01X

ביום ג', ה-16 ביולי 2024, תקיים חברת סינופסיס (Synopsys) את חלקו השני של הוובינר על פתרון Silicon.da של החברה, שהוא פתרון ה-Silicon Lifecycle Management (SLM) האינטגרטיבי הראשון המיועד להתמודד עם אתגרי ה-post-silicon של רכיבים מתקדמים. ההדרכה המקוונת תתקיים בשעה 20:00 לפי שעון ישראל תחת הכותרת: Maximize Productivity with Deep Insights into PPA Trajectories.

The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da.

We’ll show you how to leverage vast datasets and how the Synopsys Design.da solution performs analysis to identify PPA bottlenecks and the root-cause. The solution automatically classifies design trends, identifies limitations, and provides prescriptive guided root-cause analysis across the entire design flow.

Speaker: Jim Schultz, senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification, design planning and design implementation on CPUs, networking and security chips. As a product engineer, he has supported design implementation, design planning and package design at various EDA companies.

למידע נוסף ורישום: Deep Insights into PPA

ביום ג', ה-4 ביוני 2024, תקיים חברת סינופסיס (Synopsys) וובינר ראשון מסוגו אשר יציג את פתרון Silicon.da של החברה, שהוא פתרון ה-Silicon Lifecycle Management (SLM) האינטגרטיבי הראשון המיועד להתמודד עם אתגרי ה-post-silicon של רכיבים מתקדמים. ההדרכה המקוונת תתקיים בשעה 20:00 לפי שעון ישראל ותתקיים תחת הכותרת: The First Integrated SLM Analytics Solution from Design Through Manufacturing.

Today’s advanced node chip designs are faced with many new complexities which require more verification, more validation and more analysis. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design, test and manufacturing (petabytes), analyze the data, and provide actionable insights on that data.

Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges of advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle.

Speakers: Anti Tseng (photo below, left), Senior Manager at MediaTek. His current focus is to enable smooth mass production of first advanced process node by exploring next-generation DFT architecture, ATPG & diagnosis flow, and AI-based data analysis. Guy Cortez, principal product manager at Synopsys.

למידע נוסף ורישום:

SLM Analytics Solution from Design Through Manufacturing